Senior Staff Engineer Digital Design (f/m/div)
... digital design (SystemVerilog), verification, simulation, synthesis and related sign-off checksDefine ... on RTL and gate-level, synthesis, equivalence checking, CDCKnowledge of SystemC, ...
... digital design (SystemVerilog), verification, simulation, synthesis and related sign-off checksDefine ... on RTL and gate-level, synthesis, equivalence checking, CDCKnowledge of SystemC, ...
... and design constraints to perform synthesis, dft insertion and static timing ... in developing design constraints and Synthesis scripts (Synopsys DC) Proficiency in ...
... and design constraints to perform synthesis, dft insertion and static timing ... in developing design constraints and Synthesis scripts (Synopsys DC)Proficiency in ...
... digital design (SystemVerilog), verification , simulation , synthesis and related sign-off checks ... on RTL and gate-level , synthesis , equivalence checking , CDC Knowledge of ...
... RTL design, ensuring robust logic synthesis and running static timing analysisExecute ...
... RTL design, ensuring robust logic synthesis and running static timing analysis ...
... RTL design, ensuring robust logic synthesis and running static timing analysis ...