Internship: Lab Verification Engineer in the AMS Lab of the Development Center Villach (f/m/div)
... to the fully verified product layout which ensures high quality manufacturing ...
... to the fully verified product layout which ensures high quality manufacturing ...
... expertise in analog design and layout particularly in BCD processes Good ...
... in der SPS-Programmierung mit Siemens S7 und oder TIA PortalKenntnisse ...