Design Application Engineer for Mixed-Signal IC development (f/m/div)
... ) Knowledge of design languages: System Verilog and or VHDL Strong experience ...
... ) Knowledge of design languages: System Verilog and or VHDL Strong experience ...
... ) Knowledge of design languages : System Verilog and or VHDL Strong experience ...
... know-how SPICE, VHDL, (System)Verilog Solid programming skills (e.g. ...