Principal Engineer Mixed Signal Verification (f/m/div)
... as know-how in SPICE, VHDL, (System)VerilogGood communication skills and ...
... as know-how in SPICE, VHDL, (System)VerilogGood communication skills and ...
... how in HDL System Verilog VHDL and Modell and Simulator knowledge ...
... System Verilog and or Verilog VHDL for RTL design and verification ...
... HDL e.g. System Verilog VHDL and Modell and Simulator knowledge ...